This invention relates to an integrated circuit having a multi-layer interconnection structure manufactured using a silicon gate process.
An arithmetic operation processing system such as a microcomputer or an electronic type minicomputer is equipped with a program memory comprised of a ROM (Read Only Memory) or a RAM (Random Access Memory) which is adapted to initially store a program prior to generation of the system. The program is read out of the program memory by the operation of, for example, a key switch. The program then is decoded by an instruction decoder (one type of ROM) to provide various control signals.
FIG. 1 is a block diagram showing an arrangement of the above-mentioned instruction decoder. For a single channel MOS FET the instruction decoder is usually comprised of a two-stage static ROM structure such as a NAND-ROM 1 and NAND-ROM 2, or a NOR-ROM 1 and NOR-ROM 2, as shown in FIG. 1. Now suppose that an arithmetic operation system is to be formed into a C-MOS (Complementary MOS) configuration. In this case, a static structure is difficult to obtain in view of the size of a chip. In the case of the C-MOS configuration, the instruction decoder takes a dynamic type NAND-ROM configuration as shown in FIG. 2. The instruction decoder as shown in FIG. 2 comprises a P-channel MOS FET Q.sub.P adapted to receive a clock pulse .phi. at its gate and to precharge a node S, a plurality of series-connected N-channel MOS FETs Q.sub.N adapted to receive an input signal at their gate and forming a NAND logic, a plurality of N-channel MOS FETs Q'.sub.N for discharge control which receive the clock pulse .phi. at their gates, and an inverter INV for shaping the waveform of a signal on the node S. With the clock pulse .phi. at a low level (V.sub.SS level) the MOS FET Q.sub.P is turned ON, causing the node S to become a high level (V.sub.DD level). With the clock pulse .phi. at a high level the MOS FET Q.sub.P is rendered OFF, causing the MOS FETs Q'.sub.N to be rendered ON. If at this time all the MOS FETs Q.sub.N in one column of a series-connected array are rendered ON, the node S is discharged into a low potential level. Thus, the output of the inverter INV is inverted from a low level to a high level. If, on the other hand, even one of the MOS FETs Q.sub.N in each column is in the nonconductive state, the node S remains at a high level and the output of the inverter INV is kept at a low level.
FIG. 3 is a pattern diagram showing a conventional detailed arrangement of a NAND logic circuit section as enclosed by the broken line shown in FIG. 2. Where, for example, a P-type substrate is used as the semiconductor substrate, the NAND logic circuit section comprises an input connection layer (11, 11, . . . ) formed on the P-type substrate and made of aluminium, an N-type diffusion region 12 formed in the surface of the substrate in a direction perpendicular to the input connection layer 11 and constituting the source and drain regions of the MOS FET and part of another connection layer, and a gate connection layer 13 made of polysilicon. The input connection layer 11 is connected through a contact hole 14 to the gate connection layer 13. In FIG. 3 the MOS FET Q.sub.N is formed in a position where a circular mark is formed.
FIG. 4 is a block diagram showing the FIG. 2 instruction decoder as adopted in a one-chip microcomputer, the instruction decoder including a NAND logic circuit section of the pattern configuration as shown in FIG. 3.
The one-chip microcomputer comprises a RAM 21 for storing various data, instruction ROM 22 disposed adjacent to the RAM 21 to initially store instructions, instruction decoder 23 disposed adjacent to the instruction ROM 22 to decode an instruction supplied from the instruction ROM 22, and a pair of random logic circuits 24 and 25 each disposed on a corresponding side surface of the instruction decoder 23 and adapted to receive a decode output from the instruction decoder 23. A transfer of data is carried out between the random logic circuit 24 and the RAM 21 and an address signal is sent from the random logic circuit 25 to the instruction ROM 22.
In the conventional one-chip microcomputer, since the instruction decoder 23 has its input connection layer 11 made of aluminium as shown in FIG. 3, it is not possible to form another aluminum connection layer traversing the input connection layer 11 to transmit an output signal from the instruction decoder. That is, where an aluminium connection is multi-layered, an insulation layer between the connections must be made much thickness so as to prevent mutual interference of signals transmitted on the respective connections. The instruction decoder is characterized in that it has a greater number of output terminals than the number of input terminals, for example, 100 output terminals are provided with respect to 10 input terminals. For this reason, a longer connection distance is required between the instruction decoder 23 and the random logic circuits 24 and 25 and a broader interconnection area is involved, making the chip size of the microcomputer per se bulkier, causing a longer signal delay time. As a result, the operation speed is slowed down.